fedr27v12850l-002-02 issue date: jan. 06, 2009 MR27V12850L 8m?word 16?bit or 16m?word 8?bit page mode p2rom features 48 a1 4 47 a1 3 46 a1 2 45 a1 1 44 a1 0 43 a9 42 a8 41 a1 9 40 a2 1 39 a2 0 38 a1 8 37 a1 7 36 a7 35 a6 34 a5 33 a4 32 a3 31 a2 30 a1 29 a0 28 ce# 27 26 25 1 byte# a16 a15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48tsop(type-i) pin configuration (top view) vss vss d15/a?1 d7 d14 d6 d13 d5 d12 d4 v cc v cc a22 d11 d3 d10 d2 d9 d1 d8 d0 oe # vss vss 8,388,608-word 16-bit/16,777,216-word 8-bit electrically switchable configuration page size of 8-word x 16-bit or 16-word x 8-bit 3.0 v to 3.6 v power supply access time ..................... 85 ns max page access time ............ 30 ns max operating current ............ 50 ma max(5mhz) standby current ............... 10 a max input/output ttl compatible three-state output packages MR27V12850L-xxxtn 48-pin plastic tsop (tsop i 48-p-1220-0.50-1k) p2rom advanced technology p2rom stands for production programmed rom. this exclusive lapis semiconductor technology utilizes factory test equipment for programming the customers code into the p2rom prior to final production testing. advancements in this technology allows production costs to be equivalent to maskrom and has many advantages and added benefits over the other non-volatile technologies, which include the following; short lead time , since the p2rom is programmed at the final stage of the production process, a large p2rom inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time and minimize liability as a custom product. no mask charge , since p2roms do not utilize a custom mask for storing customer code, no mask charges apply. no additional programming charge, unlike flash and otp that require additional programming and handling costs, the p2rom already has the code loaded at the factory with minimal effect on the production throughput. the cost is included in the unit price. custom marking is available at no additional charge. pin compatible with mask rom 1/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom block diagram a 0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 ce# byte# oe# ce oe 8/ 16 switch d0 d2 d4 d6 d8 d10 d12 d14 d1 d3 d5 d7 d9 d11 d13 d15 memory cell matrix 8m 16-bit or 16m 8-bit multiplexer output buffer row decoder column decoder address buffer in 8-bit output mode, these pins are placed in a high-z state and pin d15 functions as the a-1 address pin. a?1 pin descriptions pin name functions d15 / a?1 data output / address input a0 to a22 address inputs d0 to d14 data outputs ce# chip enable input oe# output enable input byte# word / byte select input v cc power supply voltage v ss ground 2/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom function table mode ce# oe# byte# v cc d0 to d7 d8 to d14 d15/a?1 read (16-bit) l l h d out read (8-bit) l l l d out hi?z l/h h output disable l h l hi?z ? h standby h ? l 3.0 v to 3.6 v hi?z ? ? : don?t care (h or l) absolute maximum ratings parameter symbol condition value unit operating temperature under bias ta 0 to 70 c storage temperature tstg ? ?55 to 125 c input voltage v i ?0.5 to v cc +0.5 v output voltage v o ?0.5 to v cc +0.5 v power supply voltage v cc relative to v ss ?0.5 to 5 v power dissipation per package p d ta = 25c 1.0 w output short circuit current i os ? 10 ma recommended operating conditions (ta = 0 to 70c) parameter symbol condition min. typ. max. unit v cc power supply voltage v cc 3.0 ? 3.6 v input ?h? level v ih 2.2 ? v cc +0.5 ? v input ?l? level v il v cc = 3.0 to 3.6 v ?0.5 ?? ? 0.6 v voltage is relative to v ss . ? : vcc+1.5v(max.) when pulse width of overshoot is less than 10ns. ?? : -1.5v(min.) when pulse width of undershoot is less than 10ns. pin capacitance (v cc = 3.0 v, ta = 25c, f = 1 mhz) parameter symbol condition min. typ. max. unit input c in1 ? ? 10 byte# c in2 v i = 0 v ? ? 200 output c out v o = 0 v ? ? 10 pf 3/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom electrical characteristics dc characteristics (v cc = 3.0 to 3.6 v, ta = 0 to 70c) parameter symbol condition min. typ. max. unit input leakage current i li v i = 0 to v cc ? ? 10 a output leakage current i lo v o = 0 to v cc ? ? 10 a i ccsc ce# = v cc ? ? 10 a v cc power supply current (standby) i ccst ce# = v ih ? ? 1 ma v cc power supply current (read) i cca ce# = v il , oe# = v ih f=5mhz ? ? 50 ma input ?h? level v ih ? 2.2 ? v cc +0.5 ? v input ?l? level v il ? ?0.5 ?? ? 0.6 v output ?h? level v oh i oh = ?1 ma 2.4 ? ? v output ?l? level v ol i ol = 2 ma ? ? 0.4 v voltage is relative to v ss . ? : vcc+1.5v(max.) when pulse width of overshoot is less than 10ns. ?? : -1.5v(min.) when pulse width of undershoot is less than 10ns. ac characteristics (v cc = 3.0 to 3.6 v, ta = 0 to 70c) parameter symbol condition min. max. unit address cycle time t c ? 85 ? ns address access time t acc ce# = oe# = v il ? 85 ns page cycle time t pc ? 30 ? ns page access time t pac ? ? 30 ns ce# access time t ce oe# = v il ? 85 ns oe# access time t oe ce# = v il ? 30 ns t chz oe# = v il 0 20 ns output disable time t ohz ce# = v il 0 20 ns output hold time t oh ce# = oe# = v il 0 ? ns measurement conditions input signal level ....................................... 0 v/3 v input timing reference level....................... 1/2vcc output load ............................................... 50 pf output timing reference level .................... 1/2vcc output load output 50 pf (including scope and jig) 4/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom timing chart (read cycle) random access mode read cycle ce# oe# d0 to d15(word mode) t c t ce t oe t oh t chz t ohz valid data hi-z hi-z t oh valid data t acc t c t acc a -1 to a 22 ( b y te mod e ) a0 to a22 (word mode) d0 to d7(by te mode) d8 to d15 : hi-z(byte mode) page access mode read cycle a 3 to a 21 t ce t oe t acc t oh t chz t ohz hi-z hi-z d0 to d7(byte mode) d8 to d15 : hi-z(byte mode) d0 to d15(word mode) t pac t pac t pc t pc t c a-1 to a2 (byte mode) a 0 to a 2 ( word mode ) ce# oe# 5/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom package dimensions (unit: mm) notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 6/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom revision history page document no. date previous edition current edition description fedr27v12850l-02-01 may.9, 2005 ? ? final edition 1 1, 4 1, 4 change tc, tacc, tce to 85ns fedr27v12850l-002-02 jan.6, 2009 ? ? changed company logo and name to oki semiconductor 7/ 8
fedr27v12850l-002-02 MR27V12850L / p2rom 8/8 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2009 - 2011 lapis semiconductor co., ltd.
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